System profile:

The development system is a platform for students to learn CPLD/FPGA basic theory to engineering practical application, for students to learn and understand development tools, chip application, learn programming development ideas and system structure, skilful in application relevant development, through schematics, to development suitable functions, chips or systems, through single-chip microcomputer (external functions modules), to learn development ideas and structure, as well as practical development capabilities and ideas.

System structure: coral board + base board

The coral board mainly incorporates coral functions chip (FPGA/CPLD chip), necessary power supply management circuit or clock circuit, necessary signals arrangement and necessary protection circuit. It integrates various interfaces and application circuits, as well as various coral boards, for various platform structure compatibility (single-chip microcomputer, FPGA/CPLD/SOPC, ARM coral board), for various development system functions, through coral board conversion, for module circuit functions reformation, and to change training patterns and items.

Base board hardware configurations:

1. 8-bit 8-segment red LED

2. 128x240 LCD

3. 8-bit LED light

4. 8-channel pulse/switch signals input

5. 8-channel programming clock input, 0-20M clock source

6. System programming single-chip microcomputer interface, integrated with single-chip microcomputer development.

7. 1-channel buzzer output

8. 1-channel DAC output (DAC0809)

9. 1-channel ADC input (ADC0832)

10. 2-channel RS232 interface, RS485 output

11. 1-channel PS/2 keyboard, PS/2 mouse interface

12. 1-channel VGA interface

13. Multiply power supplies: 5V/3.3V/2.8V/2.5V

14. SD card interface

15. Multi-signals output sockets

Coral board description:

The coral board adopts ALTERA Cyclone II FPGA chipEP2C8, with double phase-lock loops, by ALTERA provide EDA design tools, it can compose SOPC software and hardware source, including Quartus II, SOPC Builder, Matlab and DSP Builder, NCO Compiler, with Nios users definition commands functions, can use hardware language to configure FPGA hardware source designed as various special arithmetic modules or DSP speeder, and edit NiosII commands, that is to say, users can use SOPC platform to learn and master self-construction high-speed special functional processor, CPU or DSP processor, with general chips or function modules, as a trend for electronic technology development.

The coral board is connected with base board, and all chip I/O pins can be used by users for designs, experiments, contests, or projects development.

Experiments:

1. Basic experiments

A. basic experiment B. 3/8decoder experiment

C. BCD/7-segment decoder experiment D. counters experiment

E. dynamic numeric tube scan experiment F. pulse counter experiment

G. keyboard scan experiment H. dynamic ADC monitor

I. DAC signals output

2. Development experiment

A. frequency measure experiment B. frequency synthesis experiment

C. PS2 interface read experiment D. VGA analogy scan experiment

E. RS232/485communication experiment F. LCD scan experiment

3. Integrated experiments

A. Address decoding experiment B. Bus arbitrary experiment

C. Single-chip microcomputer development experiment

D. RS232/485 experiment

E. SRAM and SDRAM scan experiment

F. full-colour VGA display and video memory control

G. Process control computer automatic control system experiment

Factory workshop: